nec electronics inc. EA-C10 2.5-volt, 0.25-micron (drawn) cmos embedded array march 1997 preliminary a12503eu1v0ds00 EA-C10 series features EA-C10 series benefits 0.25 m drawn (0.18 m l-effective) cmos process t ultra-high density cell structure with high performance advanced embedded array architecture t fast tat and high integration of embedded megafunctions available gate counts from 206k to 7 million gates t support for a wide range of high-complexity systems optimized 2.5v architecture (operates down to 1.8v) t highest speed at ultra-low power consumption significant low power dissipation of 0.14 w/mhz/gate t new application possibilities and new system solutions ultra-high pin count using 40 m pad pitch t increased i/o density to achieve smaller die sizes special power rail structure, multi-oxide process t mixed 2.5v / true 3.3v i/o for full system compatibility cell-based i/o structure including lvds, hstl, gtl+, pci t flexible adaptation to system requirements embedding of analog macros including dacs, adcs t mixed-signal design options advanced packages such as tapebga, flip chip+bga t cost-effective and state-of-the-art packaging nec?s opencad ? design environment t flexible design flow for short design times applications the EA-C10 family is ideal for applications where high density is mandatory and a short time-to-market path is required. for example, ram-dominated designs can be realized with reduced die size and a reasonable turnaround time. EA-C10 is well-suited for designs that may require rework, because the logic function portion of the design uses gate array primitives created just by the final metal masks. typical applications include engineering workstations, telecommunications systems, advanced graphics and low power applications where very high performance is required. figure 1. embedded array core integration table 1. EA-C10 series features and benefits description the high-speed 0.25?m drawn (0.18?m l-effective) EA-C10 embedded array family offers both support for embedded high-density macros as well as the short turnaround time of a gate array resulting in a time-to- market advantage. in this product, nec combines high- performance cmos gate array primitives with diffused, embedded megafunctions such as ram, rom, cpu, dsp and analog cores. EA-C10 also uses a cell-based i/o structure that allows a flexible adaptation to the system requirements. state-of- the-art interface macros for high-speed or special signaling systems are also supported, such as pci, hstl, gtl+, lvds, p-ecl, and ieee1394. analog functions like dacs, adcs and plls also can be incorporated within the i/o area. process EA-C10 asics are manufactured with nec?s advanced titanium-silicide (ti-si) process. the chip layout may use between three and five metal layers (al). as the EA-C10 asic family follows basically a gate array approach, it offers short turnaround times for silicon processing and lower development costs compared to cell-based asics. the turnaround time is kept short by fixing the embedded core locations and beginning prototype fabrication in parallel with place and route design steps. high density memory analog macro logic function cell-based i/o cells high density cell-based compiled memory gate array primitives (sea-of-gate) advanced core and analog functions gate array base master core or megafunction opencad is a registered trademark of nec electronics inc. all non-nec trademarks are the property of their respective owners.
EA-C10 2 interface macro support the EA-C10 interface area uses the cell-based (cb-c10) i/o structures that provide a variety of interface options, including both 2.5-volt and 3.3-volt full-swing interface buffers. for special applications, several high-speed i/o buffer types are available. these include 3.3-volt pci cells, agp for 66?mhz and 133 mhz applications, gtl (gunning transceiver logic), hstl (class 1,2,3,4) and pseudo- ecl (pecl) buffers. these high-speed buffers are available for special applications. table 3 summarizes the available interface options. 2.5-volt / 3.3-volt mixed i/o interfacing. although EA-C10 is a 2.5-volt optimized technology with thin gate oxide, nec offers 3.3-volt-compatible i/o interfacing. the full-swing 3.3-volt interfacing is achieved through a multi-oxide process in the i/o area. the buffers for 2.5- volt / 3.3-volt interface levels can be mixed. this is supported by the special power rail structure shown in figure 2. table 2. product outline master (pd69..) 3 layer ..101 ..102 ..103 ..104 ..105 ..107 ..109 ..111 ..112 ..113 ..114 ..115 master (pd69..) 4 layer ..121 ..122 ..123 ..124 ..125 ..127 ..129 ..131 ..132 ..133 ..134 ..135 master (pd69..) 5 layer* ..141 ..142 ..143 ..144 ..145 ..147 ..149 ..151 ..152 ..153 ..154 ..155 gate count (available) 206k 338k 497k 690k 1041k 1611k 2127k 2509k 3137k 3597k 4089k 6937k number of pads (40 m pitch) 348 444 540 636 780 972 1116 1212 1356 1452 1548 2016 utilization 80% for 3-layer metal; 85% for 4-layer metal toggle frequency (typ.) 1.1 ghz internal 59 ps (f/o = 1, l = 0 mm); 147.5 ps (f/o = 2, l = typ. average length) (f322 ) delay time input 79.9 ps (f/o = 2, l = 0 mm) (fi01) output 1.363 ns (c l = 50 pf) (fo02) consumed internal 0.14 m w/mhz/gate (2.5v); 0.07 m w/mhz/gate (1.8v) power input 1.66 m w/mhz (f/o = 2, l = 0 mm) output 167 m w/mhz (c l = 15 pf) power supply voltage 2.5 v 0.2v (operation down to 1.8v possible) operating temperature -40 to +85c interface level 2.5v / 3.3v cmos level, lvttl level, gtl+,hstl, pci, pecl technology sea-of-gates 0.25 m m (drawn) silicon gate cmos (0.18 l-effective), diffused embedded macros, 3, 4 or 5* metal layers note: *5th metal layer used for flip-chip packaging figure 2. power rail structure drawing not to scale internal core for internal power supply v dd (2.5v, 3.3v) v ddq (ex. hstl) gnd increased internal cell area i/o area for 2.5v only mixed voltage i/o area 2.5v i/o area 3.3v i/o area v d d q i / o a r e a hstl / pci interfacing. a third power rail (v ddq ) is available for interface types that require a reference voltage (such as hstl, gtl+, and agp). these buffers may also be located anywhere in the i/o area.
3 EA-C10 table 3. EA-C10 i/o buffer types buffer type options and possible combinations standard i/o pull-up 50 k w , 5 k w / pull-down 50 k w interface schmitt trigger input buffers fail safe lvcmos / lvttl level output buffers: open drain tri-state low noise (slew-rate controlled) driveability: 2.5v interface: 3, 6, 9, 12, 18, 24 ma/slot 3.3v interface: 3, 6, 9, 12, 24 ma/slot high-speed pci (3.3v, up to 64 bit / 66 mhz) i/o buffers gtl / gtl+ pecl hstl sstl lvds* agp (66 mhz and 133 mhz) ieee1394* usb* note: *under development. please check the availability of the advanced interfaces with your nearest nec design center. macro library support the embedded array approach allows the combination of high-density cores with a prototype turnaround time equal to gate arrays. megafunctions and memory blocks such as ram and rom can be embedded into the sea-of-gates area within the EA-C10 base master. the area used for the megafunctions is defined by pre-diffusion. the logical function is created by the final metalization masks. this enables the usage of a gate array master and the whole set of macros available in the cell-based technology cb- c10. cores from the bicmos family (qb-10) may also be embedded. memory macros . various kinds of memory macros are available for EA-C10. designers can select either gate array memory compilers using gate array cells or cell- based compilers which offer higher density and faster access times. cell-based type memory blocks are generated based on advanced memory compiler tools and thus ensure highest flexibility for design requirements. the available memory types are described in table 4. table 4. cmos-10 / EA-C10 memory compilers family type mode ports maximum size cmos-10/ high-speed async. 1 8 kbit EA-C10 aysnc. 2 8 kbit high-speed sync. 2 16 kbit sync. 3 16 kbit sync. 5 8 kbit EA-C10 high-density sync. 1 2k word x 32 bit sync. 2 2k word x 64 bit high-speed sync. 1 2k word x 64 bit sync. 2 4k word x 64 bit super high-speed sync. 1 4k word x 64 bit block library support EA-C10's functional blocks are designed to be backward- compatible with previous families. thus, an easy migration from previous designs is possible. the library is fully compatible with cmos-10, the 0.25?m (drawn) gate array familiy. the EA-C10 family offers a wide variety of advanced blocks, including combinational gates, shift registers, adders and counters. in addition, memory blocks such as ram and rom are provided. the EA-C10 primitive macros are available in up to four performance/power options per primitive. with a range of options available, popular design synthesis tools are able to make the optimal size/performance/power choice for each path. all memory macros can be combined with a built-in-self- test (bist) macro for easy and high-performance production testing.
EA-C10 4 resolutions of 7 to 12 bits and a frequency of 100 khz to 220 mhz for high-speed conversion. mega macros . nec offers a large set of megamacros and cores to cope with today?s system requirements. table 5 shows a subset of the macro portfolio. type description type description table 5. EA-C10 mega macro library (subset listing) cpu v30mz?: 16-bit microprocessor cpu v8xx?: 32-bit risc microcontroller (several derivates) cpu arm cpu vr4xxx?: 64-bit risc microcontroller (several derivates) datapath high-speed multiplier/accumulator dsp oak: digital signal processor dsp pine: digital signal processor dsp sprx: digital signal processor i/f peripheral 16550: uart with fifo and 16450 mode i/f peripheral 4993: 8-bit parallel i/o real-time clock i/f peripheral 71037: dma controller i/f peripheral 71051: usart, 300k bit/s, full-duplex i/f peripheral 71054: programmable timer/counter i/f peripheral 71055: programmable parallel interface (3x 8-bit) i/f peripheral 71059: interrupt controller unit i/f peripheral atm (25 mhz, 155 mhz) i/f peripheral codec (modem, voice) i/f peripheral ethernet 10/100 base i/f peripheral ieee 1284: bidirectional centronics i/f peripheral ieee1394: high speed serial bus i/f peripheral mpeg2 i/f peripheral pci controller i/f peripheral rac: rambus asic cell i/f peripheral usb: universal serial bus interface dpll digital pll (up to 250 mhz) apll analog pll (up to 500 mhz) plastic bgas with up to 672 balls can help to cope with high-complexity system requirements by providing excel- lent electrical and thermal characteristics. tape bga packages support up to 1088 balls. nec expands the package offering continuously with new advanced packages. for high-performance applications with high pin counts, the 2-layer tape bga with enhanced electrical characteristics is available. applications that require ultra-dense packages can be realized with the flip- chip package. this technique can also be used for multi- chip module (mcm) structures, where die mounting was previously necessary. packaging the advanced pad pitch of 40 m allows high-pin-count applications and gives a significant benefit for pad-limited designs. EA-C10, the new high-performance embedded array family, is supported by a variety of advanced pack- ages. for lower pin counts (up to 376 pins), the standard qfp is available, including the heat-spreader package type to improve thermal characteristics. package type maximum pin/ball count plastic bga 672 tape bga 1088 qfp 376 (0.4 mm pitch) flip-chip 2016 chip scale 500 analog macros . a variety of a/d and d/a converters will be available for analog applications. analog-to-digital converters (adcs) are under development with a bit resolution of 7 to 12 bits and a frequency of 100 khz (for general-purpose applications) up to 30 mhz. digital-to- analog converters (dacs) will also be developed with v30mz, v8xx, and vr4xxx are trademarks of nec corporation.
5 EA-C10 cad support nec takes up the challenges of the new ultra-high- density 0.25?m technology by having close relationships with leading eda vendors to fulfill the design require- ments during the whole design flow. fully supported by nec?s sophisticated opencad design framework, EA-C10 maximizes design quality and flex- ibility while minimizing asic design time. nec?s opencad system allows designers to combine the eda industry?s most popular third-party design tools with proprietary nec tools, including those for advanced floorplanner, clock tree synthesis, automatic test pattern generation (atpg), full-timing simulation, accelerated fault grading and advanced place and route algorithms. the latest opencad system is open for sign-off using standard eda tools. nec offers rtl- and sta-(static timing analysis) sign-off procedures to shorten the asic design cycle of high-complexity designs. support of high-speed systems. high-speed systems require tight control of clock skew on the chip and between devices on a printed circuit board. cb-c10 provides two features to control clock skew: the digital pll (dpll) working at frequencies up to 250 mhz for chip-to-chip skew minimization and clock tree synthesis (cts). cts ? supported by an nec proprietary design tool ? is used for clock skew management through the automatic insertion of a balanced buffer tree. the clock tree insertion method minimizes large-capacitive trunks and is especially useful with the hierarchical, synthesized design style being used for high-integration devices. rc values for actual net lengths of the clock tree are used for back annotation after place and route operations. a skew as low as 60?ps can be achieved. accurate design verification. nonlinear timing calculation is a very important requirement of the high- density, deep sub-micron asic designs. nec makes use of the increased accuracy delivered by the nonlinear table look-up delay calculation methodology and offers consistent wire load models to ensure a high accuracy of the design verification. design rule check. a comprehensive design rule check (drc) program reports design rule violations as well as chip utilization statistics for the design netlist. the generated report contains such information as net counts, total pin and gate counts, and utilization figures. layout. during design synthesis, wire load models are used to get delay estimations in a very early state of the design flow. in general, there?s no need for customers to perform the floorplanning to meet the required timing. during layout, enhanced in-place optimization (ipo) features of the layout tools and engineering change order (eco) capabilities of the synthesis tools are used to optimize critical timing paths defined by the given timing constraints. this feature can reduce the total design time. test support the EA-C10 family supports automatic test generation through a scan test methodology. it includes internal scan, boundary scan (jtag) and built-in-self-test (bist) architecture for easy and high-performance production ram testing. this allows higher fault coverage, easier testing and faster development time. test of embedded megamacros is supported from nec?s test bus concept, which allows the use of predefined test pattern sets for integrated core macros. supplemental publications this data sheet contains preliminary specifications and operational data for the EA-C10 embedded array family. additional information is available in nec?s EA-C10 design manual, block library and other related documents. please refer also to the cmos-10 and cb-c10 data sheets to get more information about 0.25?m gate array and cell-based asic products. please contact your local nec design center for additional information; see the back of this data sheet for locations and telephone numbers.
EA-C10 6 absolute maximum ratings power supply voltage, v dd 3.6 v input voltage, v i ? 2.5v input buffer 3.6 v 3.3v input buffer 4.6 v output voltage, v o 2.5v buffer 3.6 v 3.3v buffer 4.6 v latch-up current, i latch 1 a operating temperature, t opt -40 to +85c storage temperature, t stg -65 to +150c input / output capacitance v dd =v i =0 v; f=1 mhz terminal symbol typ max unit input c in 4 6 pf output c out 4 6 pf i/o c i/o 4 6 pf note: values do not include package pin capacitance. power consumption description limits unit internal cell (@ 2.5v supply voltage, loaded) 0.14 w/mhz input block (fi01, f/o=2, l=0) 1.66 w/mhz output block (f002 @ 15 pf) 167 w/mhz recommended operating conditions 2.5v buffer 3.3v buffer 3.3v pci parameter symbol min max min max min max unit power supply voltage v dd 2.3 2.7 3.0 3.6 3.0 3.6 v junction temperature t j -40 +125 -40 +125 -40 +125 c low-level input voltage v il 0 0.7 -0.5 0.3 v dd -0.5 0.3 v dd v high-level input voltage v ih 1.7 v dd 0.5 v dd v dd + 0.5 0.5 v dd v dd + 0.5 v input rise or fall time t r , t f 0 200 0 200 0 200 ns input rise or fall time, schmitt t r , t f 0 10 0 10 0 10 ms ac characteristics v dd = 2.5 v 0.2 v; t j = 0 to +125c parameter symbol best typ worst unit conditions toggle frequency f tog 2.8 2.0 1.1 ghz d-f/f; f/o = 1 delay time 2-input power - nand (f322) t pd 30.5 41.1 67.7 ps f/o = 2; l = 0 mm t pd 43.6 59.0 96.4 ps f/o = 1; l = 0.5 mm flip-flop (f611) t pd 200 278 465 ps f/o = 1; l = 0 mm t pd 242 336 558 ps f/o = 2; l = 0.5 mm t setup 170 220 340 ps ? t hold 60 50 50 ps ? input buffer (fi01) t pd 77.8 103 188 ps f/o = 1; l = 0.5 mm t pd 63.0 79.7 144 ps f/o = 2; l = 0 mm input buffer (3.3v) * t pd 190 286 510 ps f/o = 1; l = 0.5 mm t pd 173 255 451 ps f/o = 2; l = 0 mm output buffer (12 ma) 2.5v t pd 287 439 779 ps c l = 0 pf output buffer (12 ma) 2.5v t pd 932 1363 2312 ps c l = 50 pf output buffer (12 ma) 3.3v * t pd 457 659 1192 ps c l = 0 pf output buffer (12 ma) 3.3v * t pd 1386 2115 3554 ps c l = 50 pf output rise time (12 ma) t r 0.73 1.03 1.83 ns c l = 15 pf; 10-90% output fall time (12 ma) t f 0.75 0.93 1.55 ns c l = 15 pf; 10-90% note: *including delay of level shifter circuit
7 EA-C10 dc characteristics v dd = 2.5 v 0.2 v; t j = 0 to +125 c parameter symbol min typ max unit conditions quiescent current <= 2000k gates i dds 40 800 a v i = v dd or gnd > 2000k gates i dds 70 1400 a v i = v dd or gnd off-state output leakage current 2.5v output i oz 10 a v o = v dd or gnd 3.3v output i oz 10 a v o = v dd or gnd output sink current with pull-up (v o = 2.5v) i r a v pu = 3.3 v, r pu =2k w output sink short circuit current i os -250 ma v o = gnd input leakage current regular i i 10 -4 10 a v i = v dd or gnd 50 k w pull-up i i tbd a v i = gnd 5 k w pull-up i i tbd ma v i = gnd 50 k w pull-down i i tbd a v i = v dd pull-up resistor 50 k w pull-up r pu tbd k w 5 k w pull-up r pu tbd k w 50 k w pull-down r pd tbd k w low-level output current 2.5v buffers 3 ma i ol 11.0 8.8 5.2 ma v ol = 0.4v 6 ma i ol 22.3 17.6 11.5 ma v ol = 0.4v 9 ma i ol 33.5 26.5 15.8 ma v ol = 0.4v 12 ma i ol 44.5 35.3 21.2 ma v ol = 0.4v 18 ma i ol 66.7 52.9 31.7 ma v ol =0.4v 24 ma i ol 88.7 70.5 42.3 ma v ol = 0.4v 3.3v buffers (full-swing) 3 ma i ol 20.5 14.5 8.3 ma v ol = 0.4v 6 ma i ol 30.3 21.7 12.5 ma v ol = 0.4v 9 ma i ol 40.5 29.0 16.7 ma v ol = 0.4v 12 ma i ol 46.8 36.0 20.8 ma v ol = 0.4v low-level output voltage 2.5v buffers v ol 0.1 v i ol = 0 ma 3.3v buffers v ol 0.1 v i ol = 0 ma high-level output voltage 2.5v buffers v oh v dd - 0.1 v i oh = 0 ma 3.3v buffers v oh v dd - 0.1 v i oh = 0 ma
EA-C10 8 for literature, call toll-free 7 a.m. to 6 p.m. pacific time : 1-800-366-9782 or fax your request to: 1-800-729-9288 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics inc. (necel). the information in this document is subject to change without notice. all devices sold by necel are covered by the provisions appearing in necel terms and conditions of sales only. including the limitation of liability, warranty, and patent provisions. necel makes no warranty, express, statutory, implied or by description, regarding information set forth herein or regarding the freedom of the described devices from patent infringement. necel assumes no responsibility for any errors that may appear in this document. necel makes no commitments to update or to keep current information contained in this document. the devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. ?standard? quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, and other consumer products. for automotive and transportation equipment, traffic control systems, anti-disaster and anti-crime systems, it is recommended that the customer contact the responsible necel salesperson to determine the reliabilty requirements for any such application and any cost adder. necel does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death. if customers wish to use necel devices in applications not intended by necel, customer must contact the responsible necel sales people to determine necel?s willingness to support a given application. ?1997 nec electronics inc./printed in u.s.a. document no. a12503eu1v0ds0 0 third-party design centers south central/southeast ? koos technical services, inc. 385 commerce way, suite 101 longwood, fl 32750 te l 407-260-8727 fa x 407-260-6227 ? integrated silicon systems inc. 2222 chapel hill nelson highway durham, nc 27713 te l 919-361-5814 fa x 919-361-2019 ? applied systems, inc. 1761 w. hillsboro blvd., suite 328 deerfield beach, fl 33442 te l 305-428-0534 fa x 305-428-5906 nec electronics inc. corporate headquarters 2880 scott boulevard p.o. box 58062 santa clara, ca 95052 tel 408-588-6000
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